1. Field of the Invention
The present invention relates to an IC tester for testing an integrated circuit (IC), and particularly to an IC tester that efficiently tests an integrated circuit whose output signal rises and falls at different timing.
2. Description of the Prior Art
Internal circuits of some integrated circuits (ICs) operate in synchronism with clock signals. These ICs are called clock synchronous ICs. Among them, some involve output and input signals that are also synchronous with the clock signals. The clock synchronous ICs are classified into two kinds. One operates in synchronism with a rise of the clock signals, and the other with a fall of the clock signal.
These ICs are usually tested with an IC tester. The test is generally classified into a function test, an AC characteristic test, and a DC characteristic test. The function test of the clock synchronous IC is carried out on each pin of the IC at a predetermined timing by comparing an expected value prepared for every clock cycle with an output signal from the pin of the IC. An ordinary IC provides two or three output values, i.e., a high level value and a low level value, or in addition to them, a high impedance value.
A conventional IC tester for testing the clock synchronous IC that provides two output levels will be explained with reference to FIGS. 1 and 2.
FIG. 1 is a block diagram showing the conventional IC tester involving an IC to be tested (DUT, device under test) 10, a signal line 20, a voltmeter 30, a signal line 40, a decision circuit 50 for determining a pass or a fail in the test, a signal line 70 for indicating a timing (hereinafter referred to as a strobe position) for comparing a tested output of the DUT 10 with an expected value, a signal line 80 for transferring the expected value, a signal line 100 for transferring a result of the decision circuit 50, and an indicator 110 for displaying the output of the decision circuit 50 to show an agreement or a disagreement of the tested output with the expected value.
The output of the DUT 10 is supplied to the voltmeter 30 through the signal line 20. The voltmeter 30 measures the voltage of the output and provides the measured result to the decision circuit 50 through the signal line 40. The decision circuit 50 receives the output of the voltmeter 30, a strobe position through the signal line 70, and the expected value (a high level value or a low level value) as well as voltage information corresponding to the expected value through the signal line 80. The decision circuit 50 compares the output of the voltmeter 30 with the expected value (a reference voltage) provided through the signal line 80 at the strobe position provided through the signal line 70, and determines a pass or a fail. Thereafter, the decision circuit 50 provides a result of the decision to the indicator 110 through the signal line 100, so that the indicator 110 may display the result.
FIG. 2 shows changes in the output signal of the DUT 10 and timing relations between the output signal and the clock signal. A fall of the output signal of the DUT 10 is in synchronism with a fall of the clock signal, and a rise of the output signal is in synchronism with a rise of the clock signal.
The conventional IC tester can allocate only one kind of strobe positions. When the strobe positions are set as indicated with white triangles in FIG. 2, expected values at the respective strobe positions will be H, H, L, H, and H. When the strobe positions are set as indicated with black triangles, expected values at the respective strobe positions will be H, L, L, H, and H.
As shown in FIG. 2, the output signal of the DUT 10 falls to a low level in the latter half of a second period of the clock signal. At this moment, the expected value at the strobe position of the white triangle is H. Accordingly, the low level of the output signal is first detected in a third period of the clock signal.
Even if the output signal of the DUT 10 does not fall to the low level in the latter half of the second period of the clock signal due to a malfunction of the DUT 10, the DUT 10 may be determined to be normally operating if the output signal of the DUT 10 falls to the low level before the first half of the third period of the clock signal as indicated with a dotted line "a". In this case, therefore, it is preferable to shift the strobe position to the latter half of each period of the clock signal as indicated with the black triangles.
This shift is not preferable, however, when the output signal rises at a fourth period of the clock signal. Even if the output signal delays to rise due to some abnormality as indicated with a dotted line "b", this abnormality will not be distinguished from a normal operation.
In this way, the conventional IC tester hardly determines in one time of operation whether or not the output signal of the DUT 10 rises and falls at a prescribed timing, and must test the output signal twice by changing the expected values and strobe positions.
These problems of the conventional IC tester happen not only in testing the clock synchronous ICs explained above but also in testing clock asynchronous ICs.
In this way, when testing ICs involving an output signal that rises and falls at different timing, the conventional IC tester uses a common strobe position both for the rises and the falls of the output signal, so that two different test patterns must be prepared one for the rises and the other for the falls. This greatly deteriorates the efficiency of IC testing.